Junction Level Heterogeneous Integration Of Iii V Materials With Si Cmos For Novel Asymmetric Field Effect Transistors

Driven by Moore's law, semiconductor chips have become faster, denser and cheaper through aggressive dimension scaling. The continued scaling not only led to dramatic performance improvements in digital logic applications but also in mixed-mode and/or communication applications. Moreover, size/weight/power (SWAP) restrictions on all high-performance system components have resulted in multi-functional integration of multiple integrated circuits (ICs)/dies in 3D packages/ICs by various system-level approaches. However, these approaches still possess shortcomings and in order to truly benefit from the most advanced digital technologies, the future high-speed/high power devices for communication applications need to be fully integrated into a single CMOS chip. Due to limitations in Si device performance in high-frequency/power applications as well as expensive III-V compound semiconductor devices with low integration density, heterogeneous integration of compound semiconductor materials/devices with Si CMOS platform has emerged as a viable solution to low-cost high-performance ICs. In this study, we first discuss on channel and drain engineering approaches in the state-of-the-art multiple-gate field-effect transistor to integrate III-V compound semiconductor materials with Si CMOS for improved device performance in mixed-mode and/or communication applications. Then, growth, characterization and electrical analysis on small-area (diameter

Fundamentals of III-V Semiconductor MOSFETs presents the fundamentals and current status of research of compound semiconductor metal-oxide-semiconductor field-effect transistors (MOSFETs) that are envisioned as a future replacement of silicon in digital circuits. The material covered begins with a review of specific properties of III-V semiconductors and available technologies making them attractive to MOSFET technology, such as band-engineered heterostructures, effect of strain, nanoscale control during epitaxial growth. Due to the lack of thermodynamically stable native oxides on III-V's (such as SiO2 on Si), high-k oxides are the natural choice of dielectrics for III-V MOSFETs. The key challenge of the III-V MOSFET technology is a high-quality, thermodynamically stable gate dielectric that passivates the interface states, similar to SiO2 on Si. Several chapters give a detailed description of materials science and electronic behavior of various dielectrics and related interfaces, as well as physics of fabricated devices and MOSFET fabrication technologies. Topics also include recent progress and understanding of various materials systems; specific issues for electrical measurement of gate stacks and FETs with low and wide bandgap channels and high interface trap density; possible paths of integration of different semiconductor materials on Si platform.

Market forces are creating a strong need to make value-added enhancements to silicon (Si) complementary metal-oxide semiconductor (CMOS) integrated circuit (IC) technology. One approach to achieve this goal is through continued scaling following Moore's law. With the future of device scaling being relatively uncertain in the next 10-20 years, it is important to find new ways to add value to CMOS. Theoretical projections show that monolithic three-dimensional (3D) integration of compound semiconductor (CS) devices can enhance the performance and functionality of future CMOS-based IC's. This becomes increasingly important with continued scaling. With each new technology node the interconnect pitch is reduced, increasing the RC delay. The net result is an increase in response time between circuit components, resulting in a greater need for 3D integration to minimize the length of the contact lines between CMOS and other non-digital functionalities. To achieve this complex goal, a flexible heterogeneous integration strategy is required that can incorporate a diverse selection of materials all onto a single substrate. Electric-field assisted assembly is a promising technique that allows for fast, low temperature and versatile integration of a large variety of materials onto alternative substrates. In this technique, particles can be assembled from solution at high yields, achieving sub-micron alignment registration to predefined features on the substrate. The approach is not limited by mismatch in coefficient of thermal expansion (CTE) and lattice constant, offering the flexibility to apply materials at the device layer, or any subsequent layer in the CMOS backend. In this thesis research, electric-field assisted assembly of micron-sized compound semiconductor (CS) sheets is studied through a combination of experiment and finite element method (FEM) modeling. This work presents a clear picture of charge distribution within an assembled particle on the substrate, and uses the model to accurately predict the preferred assembly position. The assembly position is confirmed experimentally, demonstrating reproducible sub-micron alignment accuracy with respect to patterned features on a substrate. Through a combination of electric-field assisted assembly and top down fabrication, a novel heterogeneous integration strategy is demonstrated. As a proof of concept, this technique is used to create In0.53Ga0.47As fin geometry p+-i-n+ junctions directly on Si substrates. The as-etched fin devices are not rectifying, but with annealing at 350oC in N2 for 20 minutes, the electrical properties are restored. This process is further developed to implement fin tunnel field-effect transistors (TFETs) and metal-oxide semiconductor field-effect transistors (MOSFETs) integrated on Si. While dry etch-induced damage degrades the TFET device performance, fin MOSFETs show considerably better device performance due to their majority carrier device operation. Fin MOSFETs have a subthreshold slope of 280mV/decade and an on/off ratio of ~103 at 100mV. Through technology aided computer design (TCAD) simulations, it is shown that MOSFET performance can be improved by implementing an optimized doping design. To further emphasize the versatility of this heterogeneous integration strategy, solution-synthesized germanium selenide (GeSe) particles are assembled onto Si substrates. GeSe offers promise for phase change memory applications and non-toxic solar cells, due to its bandgap in the visible spectrum and use of earth-abundant non-toxic elements. GeSe nanobelts are measured both with 2-pt and 4-pt single particle measurements, and a resistivity of 360 [omega]-cm is determined. This integration strategy is a reproducible technique for single particle measurements of solution-synthesized materials, something significantly lacking in the field. With such a technique, solution-synthesized particles can be evaluated for their use in future device applications.

High Mobility Materials for CMOS Applications provides a comprehensive overview of recent developments in the field of (Si)Ge and III-V materials and their integration on Si. The book covers material growth and integration on Si, going all the way from device to circuit design. While the book's focus is on digital applications, a number of chapters also address the use of III-V for RF and analog applications, and in optoelectronics. With CMOS technology moving to the 10nm node and beyond, however, severe concerns with power dissipation and performance are arising, hence the need for this timely work on the advantages and challenges of the technology. Addresses each of the challenges of utilizing high mobility materials for CMOS applications, presenting possible solutions and the latest innovations Covers the latest advances in research on heterogeneous integration, gate stack, device design and scalability Provides a broad overview of the topic, from materials integration to circuits

The application of the 111-V compound semiconductors to device fabrica tion has grown considerably in the last few years. This process has been stimulated, in part, by the advancement in the understanding of the interface physics and chemistry of the III-V's. The literature on this subject is spread over the last 15 years and appears in many journals and conference proceedings. Understanding this literature requires consider able effort by the seasoned researcher, and even more for those starting out in the field or by engineers and scientists who wish to apply this knowledge to the fabrication of devices. The purpose of this book is to bring together much of the fundamental and practical knowledge on the physics and chemistry of the 111-V compounds with metals and dielectrics. The authors of this book have endeavored to provide concise overviews of these areas with many tahles ancI grarhs whic. h c. omr>are and summarize the literature. In this way, the book serves as both an insightful treatise on III-V interfaces and a handy reference to the literature. The selection of authors was mandated by the desire to include both fundamental and practical approaches, covering device and material aspects of the interfaces. All of the authors are recognized experts on III-V interfaces and each has worked for many years in his subject area. This experience is projected in the breadth of understanding in each chapter.

In recent years, research on microelectronics has been specifically focused on the proposition of efficient alternative methodologies and materials to fabricate feasible integrated circuits. This book provides a general background of thin film transistors and their simulations and constructions. The contents of the book are broadly classified into two topics: design and simulation of FETs and construction of FETs. All the authors anticipate that the provided chapters will act as a single source of reference for the design, simulation and construction of FETs. This edited book will help microelectronics researchers with their endeavors and would be a great addition to the realm of semiconductor physics.

Organic Field Effect Transistors presents the state of the art in organic field effect transistors (OFETs), with a particular focus on the materials and techniques useful for making integrated circuits. The monograph begins with some general background on organic semiconductors, discusses the types of organic semiconductor materials suitable for making field effect transistors, the fabrication processes used to make integrated Circuits, and appropriate methods for measurement and modeling. Organic Field Effect Transistors is written as a basic introduction to the subject for practitioners. It will also be of interest to researchers looking for references and techniques that are not part of their subject area or routine. A synthetic organic chemist, for example, who is interested in making OFETs may use the book more as a device design and characterization reference. A thin film processing electrical engineer, on the other hand, may be interested in the book to learn about what types of electron carrying organic semiconductors may be worth trying and learning more about organic semiconductor physics.

Silicon complementary metal-oxide-semiconductor (CMOS) technology in the past few decades has been driven by aggressive device scaling to increase performance, reduce cost and lower power consumption. However, as devices are scaled below the 100 nm region, performance gain has become increasingly difficult to obtain by traditional scaling. As we move towards advanced technology nodes, materials innovation and physical architecture are becoming the primary enabler for performance enhancement in CMOS technology rather than scaling. One class of materials that can potentially result in improved electrical performance are III-V semiconductors, which are ideal candidates for replacing the channel in Si CMOS owing to their high electron mobilities and capabilities for band-engineering. This work is aimed towards the growth and characterization of III-V semiconductor heterostructures and their application in post-Si-CMOS devices. The two main components of this study include the integration of III-V compound semiconductors on silicon for tunnel-junction Esaki diodes, and the investigation of carrier transport properties in low-power III-V n-channel FETs under uniaxial strain for advanced III-V CMOS solutions. The integration of III-V compound semiconductors with Si can combine the cost advantage and maturity of the Si technology with the superior performance of III-V materials. We have demonstrated high quality epitaxial growth of GaAs and GaSb on Si (001) wafers through the use of various buffer layers including AlSb and crystalline SrTiO3. These GaSb/Si virtual substrates were used for the fabrication and characterization of InAs/GaSb broken-gap Esaki-tunnel diodes as a possible solution for heterojunction Tunnel-FETs. In addition, the carrier transport properties of InAs 110 channels were evaluated under uniaxial strain for the potential use of strain solutions in III-V CMOS.

Advanced Field-Effect Transistors: Theory and Applications offers a fresh perspective on the design and analysis of advanced field-effect transistor (FET) devices and their applications. The text emphasizes both fundamental and new paradigms that are essential for upcoming advancement in the field of transistors beyond complementary metal–oxide–semiconductors (CMOS). This book uses lucid, intuitive language to gradually increase the comprehension of readers about the key concepts of FETs, including their theory and applications. In order to improve readers’ learning opportunities, Advanced Field-Effect Transistors: Theory and Applications presents a wide range of crucial topics: Design and challenges in tunneling FETs Various modeling approaches for FETs Study of organic thin-film transistors Biosensing applications of FETs Implementation of memory and logic gates with FETs The advent of low-power semiconductor devices and related implications for upcoming technology nodes provide valuable insight into low-power devices and their applicability in wireless, biosensing, and circuit aspects. As a result, researchers are constantly looking for new semiconductor devices to meet consumer demand. This book gives more details about all aspects of the low-power technology, including ongoing and prospective circumstances with fundamentals of FET devices as well as sophisticated low-power applications.

Heterogeneous integration uses packaging technology to integrate dissimilar chips, LED, MEMS, VCSEL, etc. from different fabless houses and with different functions and wafer sizes into a single system or subsystem. How are these dissimilar chips and optical components supposed to talk to each other? The answer is redistribution layers (RDLs). This book addresses the fabrication of RDLs for heterogeneous integrations, and especially focuses on RDLs on: A) organic substrates, B) silicon substrates (through-silicon via (TSV)-interposers), C) silicon substrates (bridges), D) fan-out substrates, and E) ASIC, memory, LED, MEMS, and VCSEL systems. The book offers a valuable asset for researchers, engineers, and graduate students in the fields of semiconductor packaging, materials sciences, mechanical engineering, electronic engineering, telecommunications, networking, etc.