Heterogeneous Integration Of Iii V And Ii Iv Semiconductor Sheets Onto Silicon Substrate Through Electric Field Assisted Assembly For Device Applications

Market forces are creating a strong need to make value-added enhancements to silicon (Si) complementary metal-oxide semiconductor (CMOS) integrated circuit (IC) technology. One approach to achieve this goal is through continued scaling following Moore's law. With the future of device scaling being relatively uncertain in the next 10-20 years, it is important to find new ways to add value to CMOS. Theoretical projections show that monolithic three-dimensional (3D) integration of compound semiconductor (CS) devices can enhance the performance and functionality of future CMOS-based IC's. This becomes increasingly important with continued scaling. With each new technology node the interconnect pitch is reduced, increasing the RC delay. The net result is an increase in response time between circuit components, resulting in a greater need for 3D integration to minimize the length of the contact lines between CMOS and other non-digital functionalities. To achieve this complex goal, a flexible heterogeneous integration strategy is required that can incorporate a diverse selection of materials all onto a single substrate. Electric-field assisted assembly is a promising technique that allows for fast, low temperature and versatile integration of a large variety of materials onto alternative substrates. In this technique, particles can be assembled from solution at high yields, achieving sub-micron alignment registration to predefined features on the substrate. The approach is not limited by mismatch in coefficient of thermal expansion (CTE) and lattice constant, offering the flexibility to apply materials at the device layer, or any subsequent layer in the CMOS backend. In this thesis research, electric-field assisted assembly of micron-sized compound semiconductor (CS) sheets is studied through a combination of experiment and finite element method (FEM) modeling. This work presents a clear picture of charge distribution within an assembled particle on the substrate, and uses the model to accurately predict the preferred assembly position. The assembly position is confirmed experimentally, demonstrating reproducible sub-micron alignment accuracy with respect to patterned features on a substrate. Through a combination of electric-field assisted assembly and top down fabrication, a novel heterogeneous integration strategy is demonstrated. As a proof of concept, this technique is used to create In0.53Ga0.47As fin geometry p+-i-n+ junctions directly on Si substrates. The as-etched fin devices are not rectifying, but with annealing at 350oC in N2 for 20 minutes, the electrical properties are restored. This process is further developed to implement fin tunnel field-effect transistors (TFETs) and metal-oxide semiconductor field-effect transistors (MOSFETs) integrated on Si. While dry etch-induced damage degrades the TFET device performance, fin MOSFETs show considerably better device performance due to their majority carrier device operation. Fin MOSFETs have a subthreshold slope of 280mV/decade and an on/off ratio of ~103 at 100mV. Through technology aided computer design (TCAD) simulations, it is shown that MOSFET performance can be improved by implementing an optimized doping design. To further emphasize the versatility of this heterogeneous integration strategy, solution-synthesized germanium selenide (GeSe) particles are assembled onto Si substrates. GeSe offers promise for phase change memory applications and non-toxic solar cells, due to its bandgap in the visible spectrum and use of earth-abundant non-toxic elements. GeSe nanobelts are measured both with 2-pt and 4-pt single particle measurements, and a resistivity of 360 [omega]-cm is determined. This integration strategy is a reproducible technique for single particle measurements of solution-synthesized materials, something significantly lacking in the field. With such a technique, solution-synthesized particles can be evaluated for their use in future device applications.

Since the invention of the integrated circuit (IC) in the late 1950s, the semiconductor industry has experienced dramatic growth driven by both technology and manufacturing improvements. Over the past 40 years, the industry's growth trend has been predicted by Moore's law, and driven by the constant electrical field scaling design methodology. While the intrinsic performance of each device improves over generations, the corresponding interconnects do not. To alleviate this interconnect issue, a three-dimensional (3D) integration concept of transforming longer side to side interconnects into shorter vertical vias by using multiple active layers has attracted much attention. The focus of this thesis is on providing the foundation for 3D heterogeneous integration by investigating methods of growing single crystal materials on the silicon platform and the subsequent low-temperature process flow, through experimental demonstration, theoretical modeling and device structure simplification. First, thin film single crystal GaAs and GaSb were grown on dielectric layers on bulk silicon substrates by the rapid melt growth (RMG) method, using both rapid thermal annealing (RTA) and laser annealing. The relationship between stoichiometry and the crystal structure is discussed according to the theoretical phase diagram and the experimental results. A modified RMG structure is also proposed and demonstrated to solve the potential issue involved in integrating the RMG method into a three-dimensional integrated circuits (3D-IC) process with thick isolation layers. In order to estimate the outcome of the crystallization and to provide further understanding of the physics behind this RMG process, compact models are derived based on classical crystallization theory. Mathematical models including the geometry, the thermal environment and the outcome of the crystallization are built. The initial cooling rate is identified as the key factor for the RMG process. With the ability of integrating multiple materials on silicon substrates, the subsequent process flows using low-temperature-fabrication or simplified device structures are proposed and evaluated to achieve high density 3D integration. A "bonding substrate/monolithic contact" approach is proposed to relieve the thermal constraint from getting the starting single crystal layer without sacrificing the interconnect performance. A low-temperature process using germanium as the channel material is also discussed. Finally, gated thin film resistor structures are designed and compared to the conventional MOSFET structure with a focus on their relative performance and process complexity trade-off for future 3D-IC implementation.

Driven by Moore's law, semiconductor chips have become faster, denser and cheaper through aggressive dimension scaling. The continued scaling not only led to dramatic performance improvements in digital logic applications but also in mixed-mode and/or communication applications. Moreover, size/weight/power (SWAP) restrictions on all high-performance system components have resulted in multi-functional integration of multiple integrated circuits (ICs)/dies in 3D packages/ICs by various system-level approaches. However, these approaches still possess shortcomings and in order to truly benefit from the most advanced digital technologies, the future high-speed/high power devices for communication applications need to be fully integrated into a single CMOS chip. Due to limitations in Si device performance in high-frequency/power applications as well as expensive III-V compound semiconductor devices with low integration density, heterogeneous integration of compound semiconductor materials/devices with Si CMOS platform has emerged as a viable solution to low-cost high-performance ICs. In this study, we first discuss on channel and drain engineering approaches in the state-of-the-art multiple-gate field-effect transistor to integrate III-V compound semiconductor materials with Si CMOS for improved device performance in mixed-mode and/or communication applications. Then, growth, characterization and electrical analysis on small-area (diameter

Heterogeneous integration uses packaging technology to integrate dissimilar chips, LED, MEMS, VCSEL, etc. from different fabless houses and with different functions and wafer sizes into a single system or subsystem. How are these dissimilar chips and optical components supposed to talk to each other? The answer is redistribution layers (RDLs). This book addresses the fabrication of RDLs for heterogeneous integrations, and especially focuses on RDLs on: A) organic substrates, B) silicon substrates (through-silicon via (TSV)-interposers), C) silicon substrates (bridges), D) fan-out substrates, and E) ASIC, memory, LED, MEMS, and VCSEL systems. The book offers a valuable asset for researchers, engineers, and graduate students in the fields of semiconductor packaging, materials sciences, mechanical engineering, electronic engineering, telecommunications, networking, etc.

Since the invention of the integrated circuit (IC) in the late 1950s, the semiconductor industry has experienced dramatic growth driven by both technology and manufacturing improvements. Over the past 40 years, the industry's growth trend has been predicted by Moore's law, and driven by the constant electrical field scaling design methodology. While the intrinsic performance of each device improves over generations, the corresponding interconnects do not. To alleviate this interconnect issue, a three-dimensional (3D) integration concept of transforming longer side to side interconnects into shorter vertical vias by using multiple active layers has attracted much attention. The focus of this thesis is on providing the foundation for 3D heterogeneous integration by investigating methods of growing single crystal materials on the silicon platform and the subsequent low-temperature process flow, through experimental demonstration, theoretical modeling and device structure simplification. First, thin film single crystal GaAs and GaSb were grown on dielectric layers on bulk silicon substrates by the rapid melt growth (RMG) method, using both rapid thermal annealing (RTA) and laser annealing. The relationship between stoichiometry and the crystal structure is discussed according to the theoretical phase diagram and the experimental results. A modified RMG structure is also proposed and demonstrated to solve the potential issue involved in integrating the RMG method into a three-dimensional integrated circuits (3D-IC) process with thick isolation layers. In order to estimate the outcome of the crystallization and to provide further understanding of the physics behind this RMG process, compact models are derived based on classical crystallization theory. Mathematical models including the geometry, the thermal environment and the outcome of the crystallization are built. The initial cooling rate is identified as the key factor for the RMG process. With the ability of integrating multiple materials on silicon substrates, the subsequent process flows using low-temperature-fabrication or simplified device structures are proposed and evaluated to achieve high density 3D integration. A "bonding substrate/monolithic contact" approach is proposed to relieve the thermal constraint from getting the starting single crystal layer without sacrificing the interconnect performance. A low-temperature process using germanium as the channel material is also discussed. Finally, gated thin film resistor structures are designed and compared to the conventional MOSFET structure with a focus on their relative performance and process complexity trade-off for future 3D-IC implementation.

This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, compatible substrate platforms and processing approaches must be developed. The Silicon on Lattice Engineered Silicon (SOLES) substrate allows monolithic integration. It is a Si substrate with embedded III-V template layer, which supports epitaxial IIIV device growth, consistent with present II-V technology. The structure is capped with a silicon-on-insulator (SOI) layer, which enables processing of CMOS devices. The processes required for fabricating and utilizing SOLES wafers which have Ge or InP as the III-V template layers are explored. Allowable thermal budgets are important to consider because the substrate must withstand the thermal budget of all subsequent device processing steps. The maximum processing temperature of Ge SOLES is found to be limited by its melting point. However, Ge diffuses through the buried Si0 2 and must be contained. Solutions include 1) limiting device processing thermal budgets, 2) improving buried silicon dioxide quality and 3) incorporating a silicon nitride diffusion barrier. InP SOLES substrates are created using wafer bonding and layer transfer of silicon, SOI and InP-on-Si wafers, established using a two-step growth method. Two different InP SOLES structures are demonstrated and their allowable thermal budgets are investigated. The thermal budgets appear to be limited by low quality silicon dioxide used for wafer bonding. For ultimate integration, parallel metallization of the III-V and CMOS devices is sought. A method of making ohmic contact to III-V materials through Si encapsulation layers, using Si CMOS technology, is established. The metallurgies and electrical characteristics of nickel silicide structures on Si/III-V films are investigated and the NiSi/Si/III-V structure is found to be optimal. This structure is composed of a standard NiSi/Si interface and novel Si/III-V interface. Specific contact resistivity of the double hetero-interface stack can be tuned by controlling Si/IIIV band alignments at the epitaxial growth interface. P-type Si/GaAs interfaces and n-type Si/InGaAs interfaces create ohmic contacts with the lowest specific contact resistivity and present viable structures for integration. A Si-encapsulated GaAs/AlGaAs laser with NiSi front-side contact is demonstrated and confirms the feasibility of these contact structures.

This book focuses on the fundamental concepts and physical and chemical aspects of pulsed laser ablation of solid targets in liquid environments and its applications in the preparation of nanomaterials and fabrication of nanostructures. The areas of focus include basic thermodynamic and kinetic processes of laser ablation in liquids, and its applic