Clock Distribution And Timing In Vlsi Systems

. . . ????????????????????????????????? ????????????? ????????????,????? ???? ??????????? ???????????????????? ???. THUCYDIDIS HISTORIAE IV:108 C. Hude ed. , Teubner, Lipsiae MCMXIII ???????????,????? ??,? ????????????????? ???????????????????? ?????? ?????? ?????? ??? ????????? ??? ?’ ?????????? ??’ ?????????? ? ??????? ??? ????????????? ???????. ???????????????????:108 ???????????? ?????????????????????? ?. ?????????????. ????????????,????? It being the fashion of men, what they wish to be true to admit even upon an ungrounded hope, and what they wish not, with a magistral kind of arguing to reject. Thucydides (the Peloponnesian War Part I), IV:108 Thomas Hobbes Trans. , Sir W. Molesworth ed. In The English Works of Thomas Hobbes of Malmesbury, Vol. VIII I have been introduced to clock design very early in my professional career when I was tapped right out of school to design and implement the clock generation and distribution of the Alpha 21364 microprocessor. Traditionally, Alpha processors - hibited highly innovative clocking systems, always worthy of ISSCC/JSSC publi- tions and for a while Alpha processors were leading the industry in terms of clock performance. I had huge shoes to ?ll. Obviously, I was overwhelmed, confused and highly con?dent that I would drag the entire project down.

Improve the performance and reliability of synchronous digital integrated circuits with this anthology of key literature on the design and analysis of clock distribution networks for VLSI based computer and signal processing systems. Beginning with an extensive tutorial overview and bibliography, this all in one source offers substantive coverage of the most relevant issues related to the design of clock distribution networks for application to high performance synchronous design. Related topics include clock skew; automated layout of clock nets; distributed buffet and interconnect delays; clock distribution design of structured custom VLSI circuits; wafer scale integration; systolic arrays; globally asynchronous, locally synchronous systems; microwave issues; low power clocking techniques; process insensitive circuits; deterministic and probabilistic delay models; system timing specifications; clock distribution networks of well known circuits and future research in clock distribution networks. The material presented in Clock Distribution Networks in VLSI Circuits and Systems will be valuable to anyone with an interest in synchronous integrated circuits, computer design, or signal processing implementation issues.

History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de velopments in this area have been slow to reach the designers' desktops.

. . . ????????????????????????????????? ????????????? ????????????,????? ???? ??????????? ???????????????????? ???. THUCYDIDIS HISTORIAE IV:108 C. Hude ed. , Teubner, Lipsiae MCMXIII ???????????,????? ??,? ????????????????? ???????????????????? ?????? ?????? ?????? ??? ????????? ??? ?’ ?????????? ??’ ?????????? ? ??????? ??? ????????????? ???????. ???????????????????:108 ???????????? ?????????????????????? ?. ?????????????. ????????????,????? It being the fashion of men, what they wish to be true to admit even upon an ungrounded hope, and what they wish not, with a magistral kind of arguing to reject. Thucydides (the Peloponnesian War Part I), IV:108 Thomas Hobbes Trans. , Sir W. Molesworth ed. In The English Works of Thomas Hobbes of Malmesbury, Vol. VIII I have been introduced to clock design very early in my professional career when I was tapped right out of school to design and implement the clock generation and distribution of the Alpha 21364 microprocessor. Traditionally, Alpha processors - hibited highly innovative clocking systems, always worthy of ISSCC/JSSC publi- tions and for a while Alpha processors were leading the industry in terms of clock performance. I had huge shoes to ?ll. Obviously, I was overwhelmed, confused and highly con?dent that I would drag the entire project down.

A number of fundamental topics in the field of high performance clock distribution networks is covered in this book. High Performance Clock Distribution Networks is composed of ten contributions from authors at academic and industrial institutions. Topically, these contributions can be grouped within three primary areas. The first topic area deals with exploiting the localized nature of clock skew. The second topic area deals with the implementation of these clock distribution networks, while the third topic area considers more long-range aspects of next-generation clock distribution networks. High Performance Clock Distribution Networks presents a number of interesting strategies for designing and building high performance clock distribution networks. Many aspects of the ideas presented in these contributions are being developed and applied today in next-generation high-performance microprocessors.

This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling. Coverage also provides a framework for and results from implementing timing optimization algorithms in a parallel computing environment.

Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization. Timing Analysis and Optimization of Sequential Circuits covers the following topics: Algorithms for sequential timing analysis Fast algorithms for clock skew optimization and their applications Efficient techniques for retiming large sequential circuits Coupling sequential and combinational optimizations. Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.

The process of Integrated Circuits (IC) started its era of VLSI (Very Large Scale Integration) in 1970’s when thousands of transistors were integrated into one single chip. Nowadays we are able to integrate more than a billion transistors on a single chip. However, the term “VLSI” is still being used, though there was some effort to coin a new term ULSI (Ultra-Large Scale Integration) for fine distinctions many years ago. VLSI technology has brought tremendous benefits to our everyday life since its occurrence. VLSI circuits are used everywhere, real applications include microprocessors in a personal computer or workstation, chips in a graphic card, digital camera or camcorder, chips in a cell phone or a portable computing device, and embedded processors in an automobile, et al. VLSI covers many phases of design and fabrication of integrated circuits. For a commercial chip design, it involves system definition, VLSI architecture design and optimization, RTL (register transfer language) coding, (pre- and post-synthesis) simulation and verification, synthesis, place and route, timing analyses and timing closure, and multi-step semiconductor device fabrication including wafer processing, die preparation, IC packaging and testing, et al. As the process technology scales down, hundreds or even thousands of millions of transistors are integrated into one single chip. Hence, more and more complicated systems can be integrated into a single chip, the so-called System-on-chip (SoC), which brings to VLSI engineers ever increasingly challenges to master techniques in various phases of VLSI design. For modern SoC design, practical applications are usually speed hungry. For instance, Ethernet standard has evolved from 10Mbps to 10Gbps. Now the specification for 100Mbps Ethernet is on the way. On the other hand, with the popularity of wireless and portable computing devices, low power consumption has become extremely critical. To meet these contradicting requirements, VLSI designers have to perform optimizations at all levels of design. This book is intended to cover a wide range of VLSI design topics. The book can be roughly partitioned into four parts. Part I is mainly focused on algorithmic level and architectural level VLSI design and optimization for image and video signal processing systems. Part II addresses VLSI design optimizations for cryptography and error correction coding. Part III discusses general SoC design techniques as well as other application-specific VLSI design optimizations. The last part will cover generic nano-scale circuit-level design techniques.