Vhsic Very High Speed Integrated Circuits

This report presents a description and final account of the VHSIC program during its ten years of successfully developing advanced integrated circuit technologies and products for military systems. The new technologies and the products that VHSIC has produced have steadily found their way not only into the defense systems but also into the commercial industrial base. They provide the reservoir from which new system capabilities are emerging and a foundation upon which continual further advances are being made. Over the course of the past decade, the VHSIC program has been active in the development of new materials, new circuit design concepts, advanced fabrication processes, new manufacturing equipment, higher levels of radiation hardening, new data interface standards and specifications, and improved techniques for built-in-test and maintainability. The VHSIC Hardware Description Language and other design automation tools have broken through major integrated circuit complexity barriers and will decrease the cost and the development time of modern electronic systems. The resulting achievements have helped to produce a new level of system design and fabrication---one that approaches an integrated concept-to-system capability.

Contents--Summary; Technology Insertion; Phase 1; Phase 2: Submicron Technology; Phase 3 and Other Supporting Technologies; Information Sources; Policy; Appendices: Policy Documents, References, VHSIC Points of Contact - Government, VHSIC Contracts - Points of Contact, Exhibitors at VHSIC Conferences, Glossary.

The appropriate interconnect model has changed several times over the past two decades due to the application of aggressive technology scaling. New, more accurate interconnect models are required to manage the changing physical characteristics of integrated circuits. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnect. However, on-chip inductance is becoming more important with integrated circuits operating at higher frequencies, since the inductive impedance is proportional to the frequency. The operating frequencies of integrated circuits have increased dramatically over the past decade and are expected to maintain the same rate of increase over the next decade, approaching 10 GHz by the year 2012. Also, wide wires are frequently encountered in important global nets, such as clock distribution networks and in upper metal layers, and performance requirements are pushing the introduction of new materials for low resistance interconnect, such as copper interconnect already used in many commercial CMOS technologies. On-Chip Inductance in High Speed Integrated Circuits deals with the design and analysis of integrated circuits with a specific focus on on-chip inductance effects. It has been described throughout this book that inductance can have a tangible effect on current high speed integrated circuits. For example, neglecting inductance and using an RC interconnect model in a production 0.25 mum CMOS technology can cause large errors (over 35%) in estimates of the propagation delay of on-chip interconnect. It has also been shown that including inductance in the repeater insertion design process as compared to using an RC model improves the overall repeater solution in terms of area, power, and delay with average savings of 40.8%, 15.6%, and 6.7%, respectively. On-Chip Inductance in High Speed Integrated Circuits is full of design and analysis techniques for RLC interconnect. These techniques are compared to techniques traditionally used for RC interconnect design to emphasize the effect of inductance. emOn-Chip Inductance in High Speed Integrated Circuits will be of interest to researchers in the area of high frequency interconnect, noise, and high performance integrated circuit design.

As the complexity of microelectronic systems continuously increases, it becomes critical to develop effective tools that can cut the design time and improve the quality of design. DoD needs to develop new tools to be able to simulate large complex systems, and to fully maximize the rapid progress in high performance computing technology occurring today. The goal of this project was to develop and implement efficient paradigms for VHDL simulation on massively parallel processor machines so that we can achieve speed up of up to a hundred times compared to sequential simulation. Our research focus was on performance and behavioral level simulation. The performance model allows us to find the trade off between various hardware components and architectures. Behavioral simulations are used to prove the functional correctness of the system. The research issues involved in the project were: processor communications, synchronization, and event queue manipulation, deadlock handling, communication latency hiding, and granularity of computation. We have measured the performance of the proposed techniques on various platforms such as the IBM SP2 and SGI Origin 2000, and achieved speed ups of 31 times.

This research investigates the requirements needed to simulate VHDL electronic circuit descriptions by using an MC68020 based parallel engine. It analyzes the potential parallelism of the simulation of VHDL descriptions and presents a detailed design of the system hardware and software requirements. It presents timing models of the overall system for speedup, network operation, and synchronization. It concludes with a description of an N.2 simulation program which validates the operational characteristics of the design. (Thesis).