Vhdl Vhsic Very High Speed Integrated Circuit Hardware Description Language Hardware Simulator Using Parallel Processors

This research investigates the requirements needed to simulate VHDL electronic circuit descriptions by using an MC68020 based parallel engine. It analyzes the potential parallelism of the simulation of VHDL descriptions and presents a detailed design of the system hardware and software requirements. It presents timing models of the overall system for speedup, network operation, and synchronization. It concludes with a description of an N.2 simulation program which validates the operational characteristics of the design. (Thesis).

As the complexity of microelectronic systems continuously increases, it becomes critical to develop effective tools that can cut the design time and improve the quality of design. DoD needs to develop new tools to be able to simulate large complex systems, and to fully maximize the rapid progress in high performance computing technology occurring today. The goal of this project was to develop and implement efficient paradigms for VHDL simulation on massively parallel processor machines so that we can achieve speed up of up to a hundred times compared to sequential simulation. Our research focus was on performance and behavioral level simulation. The performance model allows us to find the trade off between various hardware components and architectures. Behavioral simulations are used to prove the functional correctness of the system. The research issues involved in the project were: processor communications, synchronization, and event queue manipulation, deadlock handling, communication latency hiding, and granularity of computation. We have measured the performance of the proposed techniques on various platforms such as the IBM SP2 and SGI Origin 2000, and achieved speed ups of 31 times.

VHDL is a comprehensive language that allows a user to deal with design complexity. Design, and the data representing a design, are complex by the very nature of a modern digital system constructed from VLSI chips. VHDL is the first language to allow one to capture all the nuances of that complexity, and to effectively manage the data and the design process. As this book shows, VHDL is not by its nature a complex language. In 1980, the U. S. Government launched a very aggressive effort to advance the state-of-the-art in silicon technology. The objective was to significantly enhance operating performance and circuit density for Very Large Scale Integration (VLSI) silicon chips. The U. S. Government realized that in order for contractors to be able to work together to develop VLSI products, to document the resulting designs, to be able to reuse the designs in future products, and to efficiently upgrade existing designs, they needed a common communication medium for the design data. They wanted the design descriptions to be computer readable and executable. They also recognized that with the high densities envisioned for the U. S. Government's Very High Speed Integrated Circuit (VHSIC) chips and the large systems required in future procurements, a means of streamlining the design process and managing the large volumes of design data was required. Thus was born the concept of a standard hardware design and description language to solve all of these problems.

The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system.

The VHSIC Hardware Description Language (VHDL) provides a standard machine processable notation for describing hardware. VHDL is the result of a collaborative effort between IBM, Intermetrics, and Texas Instruments; sponsored by the Very High Speed Integrated Cir cuits (VHSIC) program office of the Department of Defense, beginning in 1981. Today it is an IEEE standard (1076-1987), and several simulators and other automated support tools for it are available commercially. By providing a standard notation for describing hardware, especially in the early stages of the hardware design process, VHDL is expected to reduce both the time lag and the cost involved in building new systems and upgrading existing ones. VHDL is the result of an evolutionary approach to language devel opment starting with high level hardware description languages existing in 1981. It has a decidedly programming language flavor, resulting both from the orientation of hardware languages of that time, and from a ma jor requirement that VHDL use Ada constructs wherever appropriate. During the 1980's there has been an increasing current of research into high level specification languages for systems, particularly in the software area, and new methods of utilizing specifications in systems de velopment. This activity is worldwide and includes, for example, object oriented design, various rigorous development methods, mathematical verification, and synthesis from high level specifications. VAL (VHDL Annotation Language) is a simple further step in the evolution of hardware description languages in the direction of applying new methods that have developed since VHDL was designed.

This book is intended to be a working reference for electronic hardware de signers who are interested in writing VHDL models. A handbook/cookbook approach is taken, with many complete examples used to illustrate the fea tures of the VHDL language and to provide insight into how particular classes of hardware devices can be modelled in VHDL. It is possible to use these models directly or to adapt them to similar problems with minimal effort. This book is not intended to be a complete reference manual for the VHDL language. It is possible to begin writing VHDL models with little background in VHDL by copying examples from the book and adapting them to particular problems. Some exposure to the VHDL language prior to using this book is recommended. The reader is assumed to have a solid hardware design background, preferably with some simulation experience. For the reader who is interested in getting a complete overview of the VHDL language, the following publications are recommended reading: • An Introduction to VHDL: Hardware Description and Design [LIP89] • IEEE Standard VHDL Language Reference Manual [IEEE87] • Chip-Level Behavioral Modelling [ARMS88] • Multi-Level Simulation of VLSI Systems [COEL87] Other references of interest are [USG88], [DOD88] and [CLSI87] Use of the Book If the reader is familiar with VHDL, the models described in chapters 3 through 7 can be applied directly to design problems.

The purpose of this book is to introduce VHSIC Hardware Description Lan guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im plementationtechnolo~y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs.

VHDL 101 is written for Electrical Engineers and others wishing to break into FPGA design and assumes a basic knowledge of digital design and some experience with engineering ‘process’. Bill Kafig, industry expert, swiftly brings the reader up to speed on techniques and functions commonly used in VHDL (VHSIC Hardware Description Language) as well as commands and data types. Extensive simple, complete designs accompany the content for maximum comprehension. The book concludes with a section on design re-use, which is of utmost importance to today's engineer who needs to meet a deadline and lower costs per unit. *Gets you up to speed with VHDL fast, reducing time to market and driving down costs *Covers the basics including language concepts and includes complete design examples for ease of learning * Covers widely accepted industry nomenclature * Learn from "best design practices" Gets you up to speed with VHDL fast, reducing time to market and driving down costs Covers the basics including language concepts and includes complete design examples for ease of learning Covers widely accepted industry nomenclature Learn from "best design practices"

A Guide to VHDL, Second Edition is intended for the working engineer who needs to develop, document, simulate, and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL, Second Edition includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. A Guide to VHDL, Second Edition is designed as a primer and its contents are appropriate for an introductory course in VHDL. The VHDL language was updated in 1992 with some minor improvements. In most cases, the language is upward compatible. Although this book is based primarily on the VHDL 1987 standard, this new second edition indicates the significant changes in the 1992 language to assist the designer in writing upwardly compatible code.