Variation Study On Advanced Cmos Systems For Low Voltage Applications

One of the key challenges in scaling beyond 10nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage (VT) inhibits supply voltage (VCC) scaling. In this work, a comprehensive study of process variations and line edge roughness (LER)/sidewall roughness (SWR) effects in advanced CMOS devices namely Silicon (Si) Bulk n-/p-FinFETs, In0.53Ga0.47As Bulk n-FinFETs, Germanium (Ge) Bulk p-FinFETs and Gallium Antimonide-Indium Arsenide (GaSb-InAs) staggered-gap Heterojunction n-/p-Tunnel FETs (HTFETs) is presented. This study is done using three-dimensional (3D) Technology Computer Aided Design (TCAD) numerical simulations. According to the sensitivity study, FinFET and Tunnel FET (TFET) device parameters are highly susceptible to n width, WFIN, and ultra-thin body thickness, Tb, variations, respectively. Moreover, TFETs show higher variation in device than FinFETs. Additionally, a Monte Carlo study of SWR variation on n- and p-FinFETs show higher 3sigma(VTLin) of In0.53Ga0.47As Bulk n- and Ge Bulk p-FinFETs than their Si counterparts. Further, to study the variation impact on memory circuits, we also simulate 6T and 10T SRAM cells with FinFETs and HTFETs, respectively. Another key challenge with advanced CMOS devices is time-dependent VT degradation due to BTI reliability. Thus, in the second part of this work, a comparative study of Positive Bias Temperature Instability (PBTI) reliability on n-type III-V devices and Negative Bias Temperature Instability (NBTI) reliability on p-type Ge devices is presented. PBTI reliability is studied in InxGa1.

This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by which sub-threshold and gate oxide leakage currents are generated. The authors present a comprehensive review of state-of-the-art dynamic, static supply and threshold voltage scaling techniques and discuss the pros and cons of supply and threshold voltage scaling techniques.

This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reader with a deep understanding of the major random variation sources, and the characterization of each random variation source. Furthermore, the book presents various CMOS device designs to surmount the random variation in future CMOS technology, emphasizing the applications to SRAM.

Low Power Circuit Design Using Advanced CMOS Technology is a summary of lectures from the first Advanced CMOS Technology Summer School (ACTS) 2017. The slides are selected from the handouts, while the text was edited according to the lecturers talk.ACTS is a joint activity supported by the IEEE Circuit and System Society (CASS) and the IEEE Solid-State Circuits Society (SSCS). The goal of the school is to provide society members as well researchers and engineers from industry the opportunity to learn about new emerging areas from leading experts in the field. ACTS is an example of high-level continuous education for junior engineers, teachers in academe, and students. ACTS was the results of a successful collaboration between societies, the local chapter leaders, and industry leaders. This summer school was the brainchild of Dr. Zhihua Wang, with strong support from volunteers from both the IEEE SSCS and CASS. In addition, the local companies, Synopsys China and Beijing IC Park, provided support.This first ACTS was held in the summer 2017 in Beijing. The lectures were given by academic researchers and industry experts, who presented each 6-hour long lectures on topics covering process technology, EDA skill, and circuit and layout design skills. The school was hosted and organized by the CASS Beijing Chapter, SSCS Beijing Chapter, and SSCS Tsinghua Student Chapter. The co-chairs of the first ACTS were Dr. Milin Zhang, Dr. Hanjun Jiang and Dr. Liyuan Liu. The first ACTS was a great success as illustrated by the many participants from all over China as well as by the publicity it has been received in various media outlets, including Xinhua News, one of the most popular news channels in China.

Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits.

A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits. The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology, and potential problems with each type of circuit. Many design examples are used throughout, most of which have been tested with silicon implementation or employed in real-world products. This ensures that the material presented relevant to both students studying the topic as well as readers requiring a practical viewpoint. Covers CMOS voltage reference circuit design, from the basics through to advanced topics Provides an overview of basic device physics and different building blocks of voltage reference designs Features real-world examples based on actual silicon implementation Includes analytical exercises, simulation exercises, and silicon layout exercises, giving readers guidance and design layout experience for voltage reference circuits Solution manual available to instructors from the book’s companion website This book is highly useful for graduate students in VLSI design, as well as practicing analog engineers and IC design professionals. Advanced undergraduates preparing for further study in VLSI will also find this book a helpful companion text.

This book enables readers to achieve ultra-low energy digital system performance. The author’s main focus is the energy consumption of microcontroller architectures in digital (sub)-systems. The book covers a broad range of topics extensively: from circuits through design strategy to system architectures. The result is a set of techniques and a context to realize minimum energy digital systems. Several prototype silicon implementations are discussed, which put the proposed techniques to the test. The achieved results demonstrate an extraordinary combination of variation-resilience, high speed performance and ultra-low energy.

Microelectronic systems and their applications are everywhere in the current human civilization, from the simplest gadget in our everyday life to fiction-like space probes which let us see wonderful pictures of other worlds within the Solar System and beyond. The semiconductor industry has become, since its inception in the 1960s, one of the largest and growing industries with approximately a 350 billion dollars market.The central device of microelectronics is the transistor, which has experienced enormous improvements in the last half century, boosted by the economic and human investments to follow the so-called “Moore's law”, which states that the number of transistors in a chip doubles every two years. Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) has become the preferred transistor in the industry for digital applications. With the miniaturization of the transistor, a major challenge is to deal with transistor Variability, as its impact becomes more and more important with decreasing size. Two identically fabricated transistors may present highly different characteristics; when this Variability is systematic in nature, we can often find a way to eliminate it using fabrication means or model it very accurately; nevertheless, Statistical Variability is the other major component of Local Variability which is more complicated to deal with; in fact, Statistical Variability is random in nature, as it results from de granular nature of matter and also from the difficulty of control atom per atom placement in an industrial level. Then, it becomes necessary to precisely characterize and model Local Statistical Variability for Variability-aware design to better predict circuit fails from simple standard circuits to final products.The purpose of this project is to go further in the characterization means of MOSFET Local Variability by revisiting existing test structures, and to develop methods of analysis to extract the maximum of relevant information about transistor Variability sources and impact from experiments conducted on improved test structures. One important merit for the Variability characterization methods developed in this project is to enable an accurate statistical modeling of Local Variations and their impact throughout the design space; to meet the goal, the methods developed must provide statistical parameters with well-established confidence, and be suited for implementation on statistical models within the circuit design flow.To achieve this objective, this work is a common project of STMicroelectronics and IMEP-LAHC laboratory, which benefit from access to 28 nm silicon technology home design test structures and state-of-the-art characterization facilities.The project is primarily focused on local variability (in micrometer scale and below), whether of systematic or statistical nature. Nevertheless, some aspects of Intrawafer and Systematic Variations are studied when it is necessary to discriminate Local Variability from other effects.

Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100μW ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over 4.1V. - Two special chapters on analog circuit design – it studies benefits and obstacles on implemented chip prototypes with three goals: ultra- low power, wide supply voltage range, and integration with standard technologies. Alternative design approaches are pursued using bulk-input transistor stages in forward-bias operation for amplifiers, modulators, and references. - Comprehensive Appendix – with additional fundamental analysis, design and scaling guidelines, circuit implementation tables and dimensions, schematics, source code listings, bill of material, etc. The discussed prototypes and given design guidelines are tested with real vibration transducer devices. The intended readership is graduate students in advanced courses, academics and lecturers, R&D engineers.