Spurious Tone Mitigation In Fractional N Phase Locked Loops

Fractional-N phase-locked loops (PLLs) are widely used to synthesize local oscillator signals for modulation and demodulation in communication systems. Their phase error inevitably consists of both a periodic component made up of spurious tones and a random component called phase noise. Spurious tones are particularly harmful to the performance of typical communication systems, so most communication standards stipulate stringent limits on their maximum power in relevant frequency bands. High-performance PLLs generally contain noise-shaping coarse quantizers to control their output frequency. Such quantizers are a fundamental source of spurious tones in the PLL's phase error. This is because spurious tones are inevitably induced when the quantizer's quantization noise is subjected to nonlinear distortion from analog circuit imperfections. This dissertation presents a rigorous analysis of this effect and a way to mitigate it through the use of a class of digital quantizers with first and higher-order highpass shaped quantization noise which are optimized for spurious tone and phase noise mitigation. The first chapter of this dissertation presents a mathematical analysis of spurious tone generation via nonlinear distortion of quantization noise. It proves that subjecting the quantization noise running sum of a digital quantizer to a nonlinearity of a certain order will inevitably induce spurious tones, and shows the relation between such nonlinearity order and the range of values the quantization noise running sum takes. The results are general and apply to any digital quantizer. The second chapter of this dissertation presents a class of digital quantizers with optimal immunity to nonlinearity-induced spurious tones and with first-order highpass shaped quantization noise. It presents design solutions for digital quantizers with quantization noise that can be subjected to nonlinear distortion of a given order without inducing spurious tones, and relies on the results from the first chapter to prove that the presented solutions are optimal in terms of spurious tone generation. The third chapter of this dissertation presents digital quantizers with second and third-order highpass shaped quantization noise which can be optimized for either spurious tone or phase noise mitigation. These quantizers can replace the often-used delta-sigma modulators in high-performance PLLs to either improve spurious-tone performance at the expense of slightly higher PLL phase noise or lower PLL phase noise. The fourth chapter of this dissertation present an integrated circuit PLL which implements the second and third-order digital quantizers presented in the third chapter. It demonstrates record-setting spurious tone performance due to the use of these digital quantizers and to a new linearity-enhancement PLL timing scheme.

Fractional-N phase locked loops (PLL) are widely used in modern communication systems to synthesize a highly pure frequency from a lower reference frequency. Stringent requirements are often placed on the spectral purity of the synthesized frequency so that overall system-level requirements are met. Unfortunately, spurious tones are inevitable in the output signals of fractional-N PLLs, and in conventional designs they can be attenuated only with design tradeoffs that degrade other aspects of performance. This dissertation presents a PLL that utilizes a successive requantizer in conjunction with an offset current technique to suppress both the fractional and reference spurs. A passive, type-II, sampled loop filter (SLF) is also introduced to mitigate the increased reference spurs that result from the use of an offset current. Chapter 1 describes a phase-noise canceling, fractional-N PLL utilizing the techniques mentioned above. It details the system level and circuit level design and presents measured results. Chapter 2 presents a discrete-time model for a PLL utilizing the passive SLF described in Chapter 1. A mathematical basis for the model is also presented. Chapter 3 describes an integer-N, realigning PLL utilizing a relaxation oscillator and a calibration scheme to suppress the realignment spur. Realignment can suppress the noise of the voltage controlled oscillator (VCO) and hence finds application in systems utilizing non-LC based VCOs. However, implementation challenges exist with regard to the VCO and many previously published designs suffer from a large realignment spur. The use of a relaxation oscillator and the calibration scheme address these two challenges.

Delta-sigma fractional-N phase-locked loops are used to generate high quality radio-frequency signals for use in wireless applications. To reduce the phase noise inherent to these systems, a digital-to-analog converter is used to cancel the error introduced by the fractional division process, however matching between the digital-to-analog converter and the phase-locked loop circuitry place a limit on the amount of phase noise reduction that can be achieved. Furthermore, circuit non-linearity results in the appearance of spurious tones in the phase-locked loop output. This dissertation outlines a calibration technique, and a digital quantization technique that provide solutions to these two problems. The calibration technique results in improved phase noise performance by adjusting the digital-to-analog converter gain, and thus providing better matching between the phase-locked loop circuitry and digital-to-analog converter. The digital quantization technique results in no spurious tones when specified non-linearity is applied to the quantizer output sequence and error. The calibration technique was implemented in an integrated circuit, which achieves state-of-the-art performance when compared to currently published phase-locked loops and allows for all circuitry to be integrated onto a single chip. Chapter 1 presents the calibration technique, as well as a theoretical analysis of the stability. Chapter 2 presents details on the digital quantization technique, and a mathematical proof of the absence of spurious tones. In chapter 3, results from an implemented circuit are presented, which verify the behaviour of the technique presented in chapter 1.

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

This book is based on the 18 tutorials presented during the 29th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, with specific contributions focusing on analog circuits for machine learning, current/voltage/temperature sensors, and high-speed communication via wireless, wireline, or optical links. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

This book is intended for the reader who wishes to gain a solid understanding of Phase Locked Loop architectures and their applications. It provides a unique balance between both theoretical perspectives and practical design trade-offs. Engineers faced with real world design problems will find this book to be a valuable reference providing example implementations, the underlying equations that describe synthesizer behavior, and measured results that will improve confidence that the equations are a reliable predictor of system behavior. New material in the Fourth Edition includes partially integrated loop filter implementations, voltage controlled oscillators, and modulation using the PLL.

In less than one decade after their introduction into radio-frequency applications, digital fractional-N phase-locked loops (PLLs) have become a relevant topic in microelectronic research and a practical solution for products. In addition to the well-known advantages, such as their silicon area occupation scaling as technology node and their easier portability to new nodes, digital PLLs enable easy and low-cost implementation of calibration techniques, which substantially reduce spurious tones and remove other major analog impairments. In wideband PLLs, the ultimate level of spur performance is often bounded by the time resolution and the linearity of the time-to-digital converter within the digital PLL. Methods for mitigating its nonlinearity such as those based on element randomization and large-scale dithering are discussed. The use of fractional-N dividers based on digital-to-time converters, as a means to relax the design of the time-to-digital converter, is also reviewed. This concept is extended to the limit case of a single-bit time-to-digital converter, which provides best PLL noise–power trade-off with good spur performance.

Fractional-N phase-locked loop (PLL) frequency synthesizers are ubiquitous in modern communication systems, where they are used to synthesize a signal of high spectral purity from a reference signal of much lower frequency. In order to meet the requirements of wireless communication standard, strict limitation are placed on the spectral content of the synthesized signal. In recent years, PLL based on time-to-digital converters (TDC-PLLs) have been proposed that aim at moving the complexity of the design from the analog section to the digital section of the synthesizer : the advantages are a reduction in area, cost and power consumption over competing architectures based on delta-sigma modulation and charge pumps ([Delta][Sigma]-PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase noise and spurious tone performance below that of the best comparable [Delta][Sigma]-PLLs. An alternative approach is to use a delta-sigma frequency-to-digital converter ([Delta][Sigma]FDC) in place of a TDC to retain the benefits of TDC-PLLs and [Delta][Sigma]-PLLs. Chapter 1 describes a practical [Delta][Sigma] FDC based PLL in which the quantization noise is equivalent to that of a [Delta][Sigma]-PLL. It presents a linearized model of the PLL, design criteria to avoid spurious tones in the [Delta][Sigma] FDC quantization noise, and a design methodology for choosing the loop parameters in terms of standard PLL target specifications. Chapter 2 presents a multi-rate quantizing dynamic element matching (DEM) encoder for digital to analog converters (DACs) that allows a significant reduction in the encoder power consumption with respect to a conventional encoder for oversampling DEM DACs, at the expense of a minimal signal-to-noise ratio reduction. In Chapter 3, the implementation details of a [Delta][Sigma] FDC based fractional-N phase-locked loop prototype are shown. The PLL was built to showcase the capability of the architecture analyzed in Chapter 1 to comply with the most stringent wireless communication standards. The prototype extends the architecture described in Chapter 1 by including an FDC quantization noise cancelling algorithm, and an hardware efficient implementation of a multi-rate quantizing DEM encoder for digital to frequency conversion.