Spur Reduction Techniques For Fractional N Plls

Fractional-N phase locked loops (PLL) are widely used in modern communication systems to synthesize a highly pure frequency from a lower reference frequency. Stringent requirements are often placed on the spectral purity of the synthesized frequency so that overall system-level requirements are met. Unfortunately, spurious tones are inevitable in the output signals of fractional-N PLLs, and in conventional designs they can be attenuated only with design tradeoffs that degrade other aspects of performance. This dissertation presents a PLL that utilizes a successive requantizer in conjunction with an offset current technique to suppress both the fractional and reference spurs. A passive, type-II, sampled loop filter (SLF) is also introduced to mitigate the increased reference spurs that result from the use of an offset current. Chapter 1 describes a phase-noise canceling, fractional-N PLL utilizing the techniques mentioned above. It details the system level and circuit level design and presents measured results. Chapter 2 presents a discrete-time model for a PLL utilizing the passive SLF described in Chapter 1. A mathematical basis for the model is also presented. Chapter 3 describes an integer-N, realigning PLL utilizing a relaxation oscillator and a calibration scheme to suppress the realignment spur. Realignment can suppress the noise of the voltage controlled oscillator (VCO) and hence finds application in systems utilizing non-LC based VCOs. However, implementation challenges exist with regard to the VCO and many previously published designs suffer from a large realignment spur. The use of a relaxation oscillator and the calibration scheme address these two challenges.

This book is intended for the reader who wishes to gain a solid understanding of Phase Locked Loop architectures and their applications. It provides a unique balance between both theoretical perspectives and practical design trade-offs. Engineers faced with real world design problems will find this book to be a valuable reference providing example implementations, the underlying equations that describe synthesizer behavior, and measured results that will improve confidence that the equations are a reliable predictor of system behavior. New material in the Fourth Edition includes partially integrated loop filter implementations, voltage controlled oscillators, and modulation using the PLL.

Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.

Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies presents theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Extensive mathematical equations are included throughout the book to analyze both single-stage and multi-stage architectures. It has been proved that appropriately set initial conditions generate tone free output, provided that the modulator order is at least three. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. Furthermore, the book also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators. The topologies have been generalized for any interleaving number and modulator order. The book is full of design and analysis techniques and contains sufficient detail that enables readers with little background in the subject to easily follow the material in it.

Discover the essential materials for phase-locked loop circuit design, from fundamentals to practical design aspects A phase-locked loop (PLL) is a type of circuit with a range of important applications in telecommunications and computing. It generates an output signal with a controlled relationship to an input signal, such as an oscillator which matches the phases of input and output signals. This is a critical function in coherent communication systems, with the result that the theory and design of these circuits are essential to electronic communications of all kinds. Phase-Locked Loops: System Perspectives and Circuit Design Aspects provides a concise, accessible introduction to PLL design. It introduces readers to the role of PLLs in modern communication systems, the fundamental techniques of phase-lock circuitry, and the possible applications of PLLs in a wide variety of electronic communications contexts. The first book of its kind to incorporate modern architectures and to balance theoretical fundamentals with detailed design insights, this promises to be a must-own text for students and industry professionals. The book also features: Coverage of PLL basics with insightful analysis and examples tailored for circuit designers Applications of PLLs for both wireless and wireline systems Practical circuit design aspects for modern frequency generation, frequency modulation, and clock recovery systems Phase-Locked Loops is essential for graduate students and advanced undergraduates in integrated circuit design, as well researchers and engineers in electrical and computing subjects.

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

Number 12 in the successful series of Analog Circuit Design provides valuable information and excellent overviews of analogue circuit design, CAD and RF systems. The series is an ideal reference for those involved in analogue and mixed-signal design.

This book explains concepts behind fractional subsampling-based frequency synthesis that is re-shaping today’s art in the field of low-noise LO generation. It covers advanced material, giving clear guidance for development of background-calibrated environments capable of spur-free synthesis and wideband phase modulation. It further expands the concepts into the field of subsampling polar transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards.