Special Issue On High Performance Memory Systems

The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. CPU speeds are approximately doubling every eighteen months, while main memory speed doubles about every ten years. The International Tech nology Roadmap for Semiconductors (ITRS) study suggests that memory will remain on its current growth path. The ITRS short-and long-term targets indicate continued scaling improvements at about the current rate by 2016. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years. A similar growth pattern is forecast for other high-density chip areas and high-performance logic (e.g., microprocessors and application specific inte grated circuits (ASICs)). In the future, molecular devices, 64 gigabit DRAMs and 28 GHz clock signals are targeted. Although densities continue to grow, we still do not see significant advances that will improve memory speed. These trends have created a problem that has been labeled the Memory Wall or Memory Gap.

Nanoelectronics: Devices, Circuits and Systems explores current and emerging trends in the field of nanoelectronics, from both a devices-to-circuits and circuits-to-systems perspective. It covers a wide spectrum and detailed discussion on the field of nanoelectronic devices, circuits and systems. This book presents an in-depth analysis and description of electron transport phenomenon at nanoscale dimensions. Both qualitative and analytical approaches are taken to explore the devices, circuit functionalities and their system applications at deep submicron and nanoscale levels. Recent devices, including FinFET, Tunnel FET, and emerging materials, including graphene, and its applications are discussed. In addition, a chapter on advanced VLSI interconnects gives clear insight to the importance of these nano-transmission lines in determining the overall IC performance. The importance of integration of optics with electronics is elucidated in the optoelectronics and photonic integrated circuit sections of this book. This book provides valuable resource materials for scientists and electrical engineers who want to learn more about nanoscale electronic materials and how they are used. Shows how electronic transport works at the nanoscale level Demonstrates how nanotechnology can help engineers create more effective circuits and systems Assesses the most commonly used nanoelectronic devices, explaining which is best for different situations

Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy.As a result you will be able to design and emulate the entire memory hierarchy. Understand all levels of the system hierarchy -Xcache, DRAM, and disk. Evaluate the system-level effects of all design choices. Model performance and energy consumption for each component in the memory hierarchy.

Die Bandbreite und Zugriffszeit traditioneller DRAMs reicht nicht mehr aus, um mit der Geschwindigkeit moderner Mikroprozessoren Schritt zu halten. Daher baut man verstärkt Hochleistungs-Speicherchips, deren neue Generation das Thema dieses Buches bildet. Die Autorin, eine international anerkannte Spezialistin, diskutiert objektiv und herstellerunabhängig Technologien wie DDR DRAMs, CiDDR DRAMs, SL=DRAM, Direct Rambus, SSTL Interfaces und MP-DRAMs. Der aktuellste verfügbare Beitrag zu einem enorm wichtigen Thema! (12/98)

A widely read and authoritative book for hardware and software designers. This innovative book exposes the characteristics of performance-optimal single- and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution time.

This book constitutes the refereed joint proceedings of ten international workshops held in conjunction with the 4th International Symposium on Parallel and Distributed Processing and Applications, ISPA 2006, held in Sorrento, Italy in December 2006. It contains 116 papers that contribute to enlarging the spectrum of the more general topics treated in the ISPA 2006 main conference.

Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors. Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service. Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linköpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington. Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.