Reconfigurable And Adaptive Computing

Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems. The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators. The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, and a 3D ant colony routing (3D-ACR) for network-on-chip with three different 3D topologies. The final section addresses the methodology of system codesign. The book introduces a new software–hardware codesign flow for embedded systems that models both processors and intellectual property cores as services. It also proposes an efficient algorithm for dependent task software–hardware codesign with the greedy partitioning and insert scheduling method (GPISM) by task graph.

This Reconfigurable Computing (RC) or Adaptive Computing System (ACS) program focused on the development of both reconfigurable computing platforms and the associated programming support environments to demonstrate the viability of RC. This was demonstrated by exploring the ability to program RCs in a main/integrated C application program and by investigating new, partially reconfigurable technology. A Xilinx 4000 Field Programmable Gate Array (FPGA) series board and a Xilinx 6200 FPGA-based board were developed as pant of this effort. The C compiler technology was developed more for a hardware pragma-based implementation, which leveraged hardware macro libraries and worked quite effectively. The Xilinx 6200 board was interesting from the standpoint that the 6200 FPGAs are partially reconfigurable. The shortfalls of this product family include poor chip design/manufacture, resulting in the inability to utilize a good portion of the FPGA logic resources. Another shortfall is a lack of functional programming tools. In spite of these problems, the team was able to exercise the partial reconfigurability of the devices by developing programming tools of their own.

This book constitutes the refereed proceedings of the 12th International Conference on Field-Programmable Logic and Applications, FPL 2002, held in Montpellier, France, in September 2002. The 104 revised regular papers and 27 poster papers presented together with three invited contributions were carefully reviewed and selected from 214 submissions. The papers are organized in topical sections on rapid prototyping, FPGA synthesis, custom computing engines, DSP applications, reconfigurable fabrics, dynamic reconfiguration, routing and placement, power estimation, synthesis issues, communication applications, new technologies, reconfigurable architectures, multimedia applications, FPGA-based arithmetic, reconfigurable processors, testing and fault-tolerance, crypto applications, multitasking, compilation techniques, etc.

This work is a comprehensive study of the field. It provides an entry point to the novice willing to move in the research field reconfigurable computing, FPGA and system on programmable chip design. The book can also be used as teaching reference for a graduate course in computer engineering, or as reference to advance electrical and computer engineers. It provides a very strong theoretical and practical background to the field, from the early Estrin’s machine to the very modern architecture such as embedded logic devices.

The Dynamic Reconfiguration for Adaptive Computing Systems (DRACS) effort has exploited the emerging technology associated with run-time reconfigurable devices to develop system capabilities for run-time reconfiguration (RTR) of AGS hardware both in response to software control and in a data-driven manner. Using the DARPA-sponsored GSRG dynamically reconfigurable device, DRAGS has demonstrated a host-driven design and reconfiguration as well as two data-driven designs, one Finite State Machine (FSM) driven and one additional host-driven demonstration. This report describes how these can be used to develop a "virtual co-processor" that supports multiple reconfigurable computing applications residing in a single piece of hardware. One demonstration focus selected involves a subset of a realistic system scenario for parameter measurement processing in electronic warfare that can be improved through the use of dynamic reconfiguration.

Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture describes the organization of reconfigurable computing system (RCS) architecture and discusses the pros and cons of different RCS architecture implementations. Providing a solid understanding of RCS technology and where it’s most effective, this book: Details the architecture organization of RCS platforms for application-specific workloads Covers the process of the architectural synthesis of hardware components for system-on-chip (SoC) for the RCS Explores the virtualization of RCS architecture from the system and on-chip levels Presents methodologies for RCS architecture run-time integration according to mode of operation and rapid adaptation to changes of multi-parametric constraints Includes illustrative examples, case studies, homework problems, and references to important literature A solutions manual is available with qualifying course adoption. Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture offers a complete road map to the synthesis of RCS architecture, exposing hardware design engineers, system architects, and students specializing in designing FPGA-based embedded systems to novel concepts in RCS architecture organization and virtualization.

As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a computation but also about the software flow that supports the design process. The goal of this book is to help designers become comfortable with these issues, and thus be able to exploit the vast opportunities possible with reconfigurable logic.

This work is a comprehensive study of the field. It provides an entry point to the novice willing to move in the research field reconfigurable computing, FPGA and system on programmable chip design. The book can also be used as teaching reference for a graduate course in computer engineering, or as reference to advance electrical and computer engineers. It provides a very strong theoretical and practical background to the field, from the early Estrin’s machine to the very modern architecture such as embedded logic devices.