Pipeline Analog To Digital Converter Design In Scaled Cmos Technology

Pipeline analog-to-digital converters (ADCs) are typically chosen for medium-to-high-resolution and high-bandwidth applications. Nevertheless, each generation of technology scaling, strongly driven by the demand for even more powerful digital computation capabilities, continuously entails a great challenge on the precision of the interstage gain in pipeline ADCs. The inaccurate interstage gain leads to the quantization leakage error in pipeline ADCs, which degrades the signal-to-noise-and-distortion ratio (SNDR) of pipeline ADCs. This dissertation demonstrates three techniques to address the inaccurate interstage gain in pipeline ADCs. To start with, an interstage gain error shaping (GES) technique is proposed. It can substantially suppress the in-band quantization leakage error in pipeline ADCs. It works for both closed-loop and open-loop amplification. It does not require extra clock phases, long convergence time, or an interruption of the digitization, incur large power or area overhead, or pose a constraint on the input signal. A two-stage pipeline successive-approximation-register (SAR) ADC equipped with the proposed second-order GES technique in 40-nm low-power (LP) CMOS technology achieves a 75.8-dB SNDR over 12.5-MHz bandwidth while operating at 100 MS/s and consuming 1.54 mW. It achieves a 174.9-dB Schreier figure of merit (FoM). The GES-related hardware only occupies less than 2% of the total active area. Next, an enhanced interstage GES technique that adopts a digital error feedback (DEF) method to address the truncation error in the prior implementation is proposed, which can extend the interstage gain error tolerance by five times. The proposed DEF technique does not introduce additional errors as it operates purely in the digital domain. In addition, a first-order passive quantization noise shaping (NS) technique that reduces the input-pair ratio of the two-input-pair comparator by 2.7 times is proposed. The proposed passive NS technique can alleviate the noise penalty caused by using a multiple-input-pair comparator. A two-stage pipeline SAR ADC equipped with the proposed techniques in 40-nm LP CMOS technology achieves a 77.1-dB SNDR over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves a 173.7-dB Schreier FoM. Finally, the use of foreground interstage gain calibration is demonstrated to address the inaccurate interstage gain in pipeline ADCs. It is implemented in a 13-bit 40-MS/s two-stage pipeline SAR ADC. The prototype ADC is designed for the phase-II readout electronics of the ATLAS liquid argon (LAr) calorimeter. To ensure its robustness under the harsh radioactive environment, several radiation-hardened techniques are implemented. To increase its yield, foreground digital-to-analog converter (DAC) mismatch calibration is also implemented. It is implemented in 65-nm LP CMOS technology. With the foreground calibration, it achieves an effective number of bits (ENOB) better than 11.2 bits over the bandwidth of interest while consuming 17.6 mW. Besides, on-chip high-speed reference buffers are deployed to avoid the need for large decoupling capacitors and provide stable reference voltages by tracking bandgap voltage references.

This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.

This book proposes innovative circuit, architecture, and system solutions in deep-scaled CMOS and FinFET technologies, which address the challenges in maximizing the accuracy*speed/power of multi-GHz sample rate and bandwidth Analog-to-Digital Converters (ADC)s. A new holistic approach is introduced that first identifies the major error sources of a converter’ building blocks, and quantitatively analyzes their impact on the overall performance, establishing the fundamental circuit-imposed accuracy – speed – power limits. The analysis extends to the architecture level, by introducing a mathematical framework to estimate and compare the accuracy – speed – power limits of several ADC architectures and variants. To gain system-level insight, time-interleaving is covered in detail, and a framework is also introduced to compare key metrics of interleaver architectures quantitatively. The impact of technology is also considered by adding process effects from several deep-scaled CMOS technologies. The validity of the introduced analytical approach and the feasibility of the proposed concepts are demonstrated by four silicon prototype Integrated Circuits (IC)s, realized in ultra-deep-scaled CMOS and FinFET technologies. Introduces a new, holistic approach for the analysis and design of high-performance ADCs in deep-scaled CMOS technologies, from theoretical concepts to silicon bring-up and verification; Describes novel methods and techniques to push the accuracy – speed – power boundaries of multi-GHz ADCs, analyzing core and peripheral circuits’ trade-offs across the entire ADC chain; Supports the introduced analysis and design concepts by four state-of-the-art silicon prototype ICs, implemented in 28nm bulk CMOS and 16nm FinFET technologies; Provides a useful reference and a valuable tool for beginners as well as experienced ADC design engineers.

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in a wide range of applications. High-speed, medium-resolution ADCs have been implemented by various ADC architectures such as a folding ADC, a subranging ADC, and a pipeline ADC. Among them, pipeline ADCs have proven to be efficient architectures for applications such as digital communication systems, data acquisition systems and video systems. Especially, power dissipation is a primary concern in applications requiring portability. Thus, the objective of this work is to design and build a low-voltage low-power medium-resolution (8-10bits) high-speed pipeline ADC in deep sub-micron CMOS technology. The non-idealities of the circuit realization are carefully investigated in order to identify the circuit requirements for a low power circuit design of a pipeline ADC. The resolution per stage plays an important role in determining overall power dissipation of a pipeline ADC. The pros and cons of both large and small number of bits per-stage are examined. A power optimization algorithm is developed to decide more accurately which approach is better for lower power dissipation. Both identical and non-identical number of bit per-stage approaches are considered and their differences are analyzed. A low-power, low-voltage 10-bit 100Msamples/s pipeline ADC was designed and implemented in a 0.18mm CMOS process. The power consumption was minimized with the right selection of the per-stage resolution based on the result of the power optimization algorithm and by the scaling down the sampling capacitor size in subsequent stages.

This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations − going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues – from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence Design FrameWork II. As well as being a comprehensive reference to the theory, the book is also unique in that it gives special importance on practical issues, giving a detailed description of the different steps that constitute the whole design flow of sigma-delta ADCs. The book begins with an introductory survey of sigma-delta modulators, their fundamentals architectures and synthesis methods covered in Chapter 1. In Chapter 2, the effect of main circuit error mechanisms is analysed, providing the necessary understanding of the main practical issues affecting the performance of sigma-delta modulators. The knowledge derived from the first two chapters is presented in the book as an essential part of the systematic top-down/bottom-up synthesis methodology of sigma-delta modulators described in Chapter 3, where a time-domain behavioural simulator named SIMSIDES is described and applied to the high-level design and verification of sigma-delta ADCs. Chapter 4 moves farther down from system-level to the circuit and physical level, providing a number of design recommendations and practical recipes to complete the design flow of sigma-delta modulators. To conclude the book, Chapter 5 gives an overview of the state-of-the-art sigma-delta ADCs, which are exhaustively analysed in order to extract practical design guidelines and to identify the incoming trends, design challenges as well as practical solutions proposed by cutting-edge designs. Offers a complete survey of sigma-delta modulator architectures from fundamentals to state-of-the art topologies, considering both switched-capacitor and continuous-time circuit implementations Gives a systematic analysis and practical design guide of sigma-delta modulators, from a top-down/bottom-up perspective, including mathematical models and analytical procedures, behavioural modeling in MATLAB/SIMULINK, macromodeling, and circuit-level implementation in Cadence Design FrameWork II, chip prototyping, and experimental characterization. Systematic compilation of cutting-edge sigma-delta modulators Complete description of SIMSIDES, a time-domain behavioural simulator implemented in MATLAB/SIMULINK Plenty of examples, case studies, and simulation test benches, covering the different stages of the design flow of sigma-delta modulators A number of electronic resources, including SIMSIDES, the statistical data used in the state-of-the-art survey, as well as many design examples and test benches are hosted on a companion website Essential reading for Researchers and electronics engineering practitioners interested in the design of high-performance data converters integrated in nanometer CMOS technologies; mixed-signal designers.

Presenting a treatment of the subject of the pipeline analog-to-digital converter (ADC), this book emphasizes implementation techniques using CMOS switched-capacitor circuits. The core materials of the textbook include architecture, circuit building blocks, practical limitations, consideration of precision, and calibration techniques.