On Chip Temperature Sensing System For Deep Sub Micron Cmos

Integrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.

This book describes the design and implementation of energy-efficient smart (digital output) temperature sensors in CMOS technology. To accomplish this, a new readout topology, namely the zoom-ADC, is presented. It combines a coarse SAR-ADC with a fine Sigma-Delta (SD) ADC. The digital result obtained from the coarse ADC is used to set the reference levels of the SD-ADC, thereby zooming its full-scale range into a small region around the input signal. This technique considerably reduces the SD-ADC’s full-scale range, and notably relaxes the number of clock cycles needed for a given resolution, as well as the DC-gain and swing of the loop-filter. Both conversion time and power-efficiency can be improved, which results in a substantial improvement in energy-efficiency. Two BJT-based sensor prototypes based on 1st-order and 2nd-order zoom-ADCs are presented. They both achieve inaccuracies of less than ±0.2°C over the military temperature range (-55°C to 125°C). A prototype capable of sensing temperatures up to 200°C is also presented. As an alternative to BJTs, sensors based on dynamic threshold MOSTs (DTMOSTs) are also presented. It is shown that DTMOSTs are capable of achieving low inaccuracy (±0.4°C over the military temperature range) as well as sub-1V operation, making them well suited for use in modern CMOS processes.

This book describes the theory and design of high-accuracy CMOS smart temperature sensors. The major topic of the work is the realization of a smart temperature sensor that has an accuracy that is so high that it can be applied without any form of calibration. Integrated in a low-cost CMOS technology, this yields at the publication date of this book one of the most inexpensive intelligent general purpose temperature sensors in the world. The first thermometers could only be read by the human eye. The industrial revolution and the following computerization asked for more intelligent sensors, which could easily communicate to digital computers. This led to· the development of integrated temperature sensors that combine a bipolar temperature sensor and an A-to-D converter on the same chip. The implementation in CMOS technology reduces the processing costs to a minimum while having the best-suited technology to increase the (digital) intelligence. The accuracy of conventional CMOS smart temperature sensors is degraded by the offset of the read-out electronics. Calibration of these errors is quite expensive, however, dynamic offset-cancellation techniques can reduce the offset of amplifiers by a factor 100 to 1000 and do not need trimming. Chapter two gives an elaborate description of the different kinds of dynamic offset-cancellation techniques. Also a new technique is introduced called the nested chopper technique. An implementation of a CMOS nested-chopper instrumentation amplifier shows a residual offset of less than lOOn V, which is the best result reported to date.