Low-power Double-sampled Delta-sigma Modulator for Broadband Applications
Author | : Weilun Shen |
Publisher | : |
Total Pages | : 202 |
Release | : 2011 |
Genre | : Analog-to-digital converters |
ISBN | : |
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High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma ADCs are able to achieve wide-band operation and high accuracy simultaneously. At first in this thesis, two novel techniques which can be applied to high performance delta-sigma ADC design are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled delta-sigma modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Date Weighted Averaging (DWA) realization. Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion delta-sigma modulator. A second-order delta-sigma modulator was designed and simulated to verify the proposed modulator topology. Finally, design of a double-sampled broadband 12-bit delta-sigma modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques: 1. Double sampled integrator to increase the effective over-sampling ratio. 2. Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back. A 2+2 cascaded topology with 3-bit internal quantizer is used in this delta-sigma modulator to adequately suppress the quantization noise while guarantee the loop stability. This delta-sigma modulator was fabricated in a 90nm digital CMOS process and achieves an SNDR of 70dB within a 5MHz signal bandwidth. The modulator occupies a silicon area of 0.5mm2 and consumes 10mW with a supply voltage of 1.2V.