Digital Self Interference Cancellation Using Fpga For In Band Full Duplex Radios

With fast increasing demand of the wireless network, the current spectrum used for commercial wireless communication becomes very crowed. So it is critical to find an more efficient way to make the limited spectrum provide larger capacity and throughput. Full-duplex communication technology has caused much attention in the past ten years since it can double the spectrum efficiency theoretically. While the main challenge obstructing it promoting into the market is the self-interference problem in a full duplex system. This dissertation focus on the self-interference cancellation (SIC) theories. The RF impairments occurred in the practical full-duplex system will be discussed. Among them, the phase noise and I/Q imbalance are regarded as the bottleneck of the self-interference cancellation and a detailed analyzing will be included in this dissertation. The general self-interference cancellation methods can be divided into passive self-interference cancellation and active self-interference cancellation where the active cancellation can be further divided into digital cancellation, analog cancellation and hybrid cancellation. This dissertation will review the theories of the passive and active self-interference cancellation. For the analog cancellation, two models (quadratic model and affine model) will be explored to handle the I/Q imbalance and phase noise. Both of these two models are based on the blind tuning algorithm which has two procedures: training and optimizing. This dissertation will introduce the development of the algorithm. It contains the computer simulation results as well as the hardware experimental results to prove the validation of the proposed ideas.

Learn about the key technologies and state of the art in research for full-duplex communications with this comprehensive guide.

Currently deployed cellular networks use bands which have been licensed and approved by the FCC. With the developments in cellular standards Rel-10 LTE advanced which supports carrier aggregation has been established where a multiple carriers are aggregated to provide a larger bandwidth. As cellular operators explore the possibility of extending the carrier aggregation to the unlicensed spectrum in the 5GHz, current developments in creating a friendly ecosystem in unlicensed bands have been summarized which form the basis of Rel-13 LTE- Licensed Assisted Access.

In the third part of this dissertation, a novel all-analog RF interference canceler is proposed. Radio self-interference cancellation (SIC) is the fundamental enabler for full-duplex radios. While SIC methods based on baseband digital signal processing and/or beamforming are inadequate, an all-analog method is useful to drastically reduce the self-interference as the first stage of SIC. It is shown that a uniform architecture with uniformly distributed RF attenuators has a performance highly dependent on the carrier frequency. It is also shown that a new architecture with the attenuators distributed in a clustered fashion has important advantages over the uniform architecture. These advantages are shown numerically through random multipath interference channels, number of control bits in step attenuators, attenuation-dependent phases, single and multi-level structures, etc.

The demands for higher data rates continue to drive research for consumer products to develop new techniques for low-cost and long battery-life wireless radios. This dissertation explores and implements several single-chip CMOS integrated circuits which aim to enable high data rates for the new spectrum opportunity in future mm-Wave 5G radios as well as to improve the spectrum efficiency for current sub-6GHz communication systems.In the mm-Wave design, a 50-58GHz 2x2 phased-array receiver (RX) for 5G communication and radar systems is described. The RX utilizes a Gm-assisted matching network (MN) to reduce the noise figure (NF) of a conventional passive mixer-first RX by placing an extra gain of ~5dB prior to the down-conversion mixers with minimal additional components. In addition to the Gm-assisted MN, this prototype phased-array RX integrates a proposed Gm-assisted MN, mixer-first RX with translational feedback, Cartesian phase shifters as a baseband beamformer, poly-phase filters, and LO generation in TSMC 28nm CMOS, occupying a total area of 0.53mm2. This RX achieves a NF of 7dB, gain of 26dB, input P1-dB of -20dBm with an 8-GHz 3-dB BW and a S11 lower than -10dB over 22-GHz BW. Second, a novel highly-digital 2x2 phased-array receiver implemented in TSMC 28-nm CMOS with several techniques, including a feedforward noise-suppressing front-end, reconfigurable 0-3 SMASH CT-delta-sigma ADC, and digital beamformer. This proposed receiver enables the development of digital multi-beam phased-array with improved front-end NF, reduced silicon area, and low power consumption for future wireless systems. Third, a dual-mode V-band power amplifier (PA) that utilizes a reconfigurable 2/4-way power combiner is introduced to enable two discrete modes of operation and enhance the efficiency at power back-off. The power combiner employs two techniques to further improve the PA efficiency at power back-off: 1) usage of transformers with non-uniform turns ratios to reduce the difference in impedance presented to the PA cores between the two modes and 2) utilize a proposed switching scheme to eliminate the leakage inductance associated with the disabled path in back-off power mode. The 2-stage PA achieves a peak gain of 21.4dB with a fractional BW (fBW) of 22.6% (51-64GHz). At 65GHz, the PA has a Psat of +17.9dBm with an OP1dB of +13.5dBm and a peak PAE of 26.5% in full-power mode. In back-off power mode, the measured Psat, OP1dB, and peak PAE are +13.8dBm, +9.6dBm, and 18.4%, respectively. The PAE is enhanced by 6% points at a 4.5-dB back-off. The PA is capable of amplifying a 6-Gb/s 16-QAM modulated signal with an EVMrms of -20.7dB at an average Pout/PAE of +13dBm/13.6%, respectively. This PA was implemented in 16-nm FinFET, occupies a core area of 0.107mm2, and operates under a 0.95-V supply. Lastly, to improve spectrum usage of the current sub-6GHz systems, a triple-path transmitter (TX) self-interference cancellation (SIC) transceiver for full-duplex (FD) systems which achieves greater than 73dB of SIC is reported. An integrated electrical balance duplexer (EBD) is employed and works in concert with two pre- and post-LNA RF feedforward cancelers implemented as analog finite impulse response (FIR) filters to form a combined three-path cancellation architecture that achieves a deep on-chip TX SIC over a very wide bandwidth (BW). The on-chip self-interference cancellation of 72.8/70.1/65.2dB was measured by comparing integrated channel power difference at the receiver (RX) baseband (BB) output while applying orthogonal frequency-division multiplexing (OFDM) multi-carrier 64-QAM Wi-Fi packages at the transmitter input with a 20/40/80-MHz bandwidth, respectively. The receiver noise figure (NF) degradation due to the TX SI leakage improves from 8dB to 1.6dB after turning on both RF cancelers. TX SI leakage reciprocal mixing with the RX LO phase noise (PN) was also significantly reduced by 11dB up to 1-MHz offset frequency measured at RX BB output. This work integrates the whole transceiver signal path from the analog baseband to RF. The FD prototype chip is fabricated in TSMC 40nm CMOS process with a die size of 4mm2 that consumes 106mW (excluding PA). An Altera Cyclone III FPGA with ADC/DAC daughter board is used to emulate the digital baseband (BB) and executes a nearest neighbor search (NNS) algorithm to close the filter adaptation loop. The RX operates from 1.6GHz to 1.9GHz with a total noise figure of 8.09dB and an IIP3 of -17dBm while operating at the highest gain of 42dB. The TX has an output P-1dB/Psat of 10.6dBm/12.5dBm measured at the antenna port, respectively. This chip also integrates an integer-N synthesizer with a measured locking range from 3.52GHz to 4.28GHz. The synthesizer consumes 10.4mW with a phase noise performance of -117dBc/Hz measured at 1-MHz frequency offset. These four prototypes demonstrate various techniques to reduce power and area for future wireless systems, including the applications in mm-Wave front-ends for new spectrum opportunities with increased data rates as well as improved spectral efficient full-duplex radios for existing sub-6GHz bands.

An important working resource for engineers and researchers involved in the design, development, and implementation of signal processing systems The last decade has seen a rapid expansion of the use of field programmable gate arrays (FPGAs) for a wide range of applications beyond traditional digital signal processing (DSP) systems. Written by a team of experts working at the leading edge of FPGA research and development, this second edition of FPGA-based Implementation of Signal Processing Systems has been extensively updated and revised to reflect the latest iterations of FPGA theory, applications, and technology. Written from a system-level perspective, it features expert discussions of contemporary methods and tools used in the design, optimization and implementation of DSP systems using programmable FPGA hardware. And it provides a wealth of practical insights—along with illustrative case studies and timely real-world examples—of critical concern to engineers working in the design and development of DSP systems for radio, telecommunications, audio-visual, and security applications, as well as bioinformatics, Big Data applications, and more. Inside you will find up-to-date coverage of: FPGA solutions for Big Data Applications, especially as they apply to huge data sets The use of ARM processors in FPGAs and the transfer of FPGAs towards heterogeneous computing platforms The evolution of High Level Synthesis tools—including new sections on Xilinx's HLS Vivado tool flow and Altera's OpenCL approach Developments in Graphical Processing Units (GPUs), which are rapidly replacing more traditional DSP systems FPGA-based Implementation of Signal Processing Systems, 2nd Edition is an indispensable guide for engineers and researchers involved in the design and development of both traditional and cutting-edge data and signal processing systems. Senior-level electrical and computer engineering graduates studying signal processing or digital signal processing also will find this volume of great interest.