Design Of High Performance Cmos Voltage Controlled Oscillators

Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

In advanced short-channel CMOS processes, analog circuit-design poses significant challenges imposed by the low power-supply voltage, and the reduced intrinsic-gain of short channel-effects of CMOS-transistors. However, continued scaling of CMOS devices makes them faster and thus enables the design of high-speed circuits such as oscillators at lower power-levels. Voltage and current-controlled oscillators are essential building blocks for designing Delta-Sigma analog-to-digital converters (ADC) that do not require a sample and hold circuits up front. This research focuses on designing scaling-friendly, linear, low-power CMOS relaxation-oscillators for Delta-Sigma analog to digital conversion. Ring oscillators using an odd number of digital-inverters provide a simple reliable-solution, and thus are popular. So the first approach is to increase the speed (time-resolution) by simply lowering the inverter-gain using the translinear and temperature-invariant voltage-mirror circuits instead of open-loop inverters. Here two scaled-inverters are used to obtain gain exploiting the function and its functional inverse idea to obtain the required loop-gain. Here we are simply trading gain to increase speed at the expense of power. An alternative approach is to use the gyrator circuit to emulate an inductor. Two transconductors with opposite polarity current-output are needed to form a gyrator. Inverting the output-polarity is achieved using a translinear, unity-gain current-mirror achieving stability of the gyrator circuit that uses negative feedback. Using these, an LC -coupled ring-oscillator is emulated. These provide a more robust solution. Process, supply-voltage and temperature (PVT) variations are traditionally minimized by the well-established technique of negative-feedback in circuits using Bandgap reference voltage and passive elements like MIM capacitors. Thus the design of an operational current to frequency converter (OCFC) is proposed. This is inspired by the success of the notion of an operational amplifier (OPAMP) that has a very large gain. It is always configured to trade gain for obtaining linearity using negative- feedback making the feedback network set the precision of the transfer function. The OCFC uses the same idea using a switched-capacitor linear frequency-to-current detector in the feedback path to make the closed-loop tuning-curve linear, having a low temperature-coefficient. The design of a simple linear oscillator based on a traditional multivibrator-circuit is explored for two specific applications. There is a need for a medium-resolution low-speed 10-bit ADC for IOT applications. The other is for a 6-bit converter for high-speed data-communication systems. The idea is to obtain the performance requirements with no need for power-hungry digital-calibration. Manufacturability, and cost are the prime focus here. Finally, an open loop Delta-Sigma modulator designed using pseudo-differential ring oscillators is explored for low bandwidth and medium resolution analog-to-digital conversion applications. It employs a nonlinearity cancellation technique in the voltage-to-current (V/I) converter to improve resolution. Most of the circuit can be synthesized using digital toolchain except for the front-end V/I converter to reduce turn-around time. All the circuits presented in this thesis are verified at multiple process nodes ranging from 180nm to 22nm. The simulation-results presented here are mostly using the models for the 180nm TSMC process

This work covers the design of CMOS fully integrated low power low phase noise voltage controlled oscillators for telecommunication or datacommuni- tion systems. The need for low power is obvious, as mobile wireless telecommunications are battery operated. As wireless telecommunication systems use oscillators in frequency synthesizers for frequency translation, the selectivity and signal to noise ratio of receivers and transmitters depend heavily on the low phase noise performance of the implemented oscillators. Datacommunication s- tems need low jitter, the time-domain equivalent of low phase noise, clocks for data detection and recovery. The power consumption is less critical. The need for multi-band and multi-mode systems pushes the high-integration of telecommunication systems. This is o?ered by sub-micron CMOS feat- ing digital ?exibility. The recent crisis in telecommunication clearly shows that mobile hand-sets became mass-market high-volume consumer products, where low-cost is of prime importance. This need for low-cost products - livens tremendously research towards CMOS alternatives for the bipolar or BiCMOS solutions in use today.

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.

One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications. Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.

Static and Dynamic Performance Limitations for High Speed D/A Converters discusses the design and implementation of high speed current-steering CMOS digital-to-analog converters. Starting from the definition of the basic specifications for a D/A converter, the elements determining the static and dynamic performance are identified. Different guidelines based on scientific derivations are suggested to optimize this performance. Furthermore, a new closed formula has been derived to account for the influence of the transistor mismatch on the achievable resolution of the current-steering D/A converter. To allow a thorough understanding of the dynamic behavior, a new factor has been introduced. Moreover, the frequency dependency of the output impedance introduces harmonic distortion components which can limit the maximum attainable spurious free dynamic range. Finally, the last part of the book gives an overview on different existing transistor mismatch models and the link with the static performance of the D/A converter.

The book discusses the latest developments and outlines future trends in the fields of microelectronics, electromagnetics and telecommunication. It contains original research works presented at the International Conference on Microelectronics, Electromagnetics and Telecommunication (ICMEET 2018), organised by GVP College of Engineering (A), Andhra Pradesh, India. The respective papers were written by scientists, research scholars and practitioners from leading universities, engineering colleges and R&D institutes from all over the world, and share the latest breakthroughs in and promising solutions to the most important issues facing today’s society.

This book provides in-depth coverage of transformer-based design techniques that enable CMOS oscillators and frequency dividers to achieve state-of-the-art performance. Design, optimization, and measured performance of oscillators and frequency dividers for different applications are discussed in detail, focusing on not only ultra-low supply voltage but also ultra-wide frequency tuning range and locking range. This book will be an invaluable reference for anyone working or interested in CMOS radio-frequency or mm-Wave integrated circuits and systems.

Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.