Characterization Integration And Reliability Of Hfo 1tn2 And Laluo 1tn3 High K63 Metal High Kappa Metal Gate Stacks For Cmos Applications

Off state leakage current related power dominates the CMOS heat dissipation problem of state of the art silicon integrated circuits. In this study, this issue has been addressed in terms of a low-cost single wafer processing (SWP) technique using a single tool for the fabrication of high- dielectric gate stacks for sub-45 nm CMOS. A system for monolayer photoassisted deposition was modified to deposit high-quality HfO2 films with in-situ clean, in-situ oxide film deposition, and in-situ anneal capability. The system was automated with Labview 8.2 for gas/precursor delivery, substrate temperature and UV lamp. The gold-hafnium oxide-aluminum (Au-HfO2-Al) stacks processed in this system had superior quality oxide characteristics with gate leakage current density on the order of 1 x 10-12 A/cm2 @ 1V and maximum capacitance on the order of 75 nF for EOT=0.39 nm. Achieving low leakage current density along with high capacitance demonstrated the excellent performance of the process developed. Detailed study of the deposition characteristics such as linearity, saturation behavior, film thickness and temperature dependence was performed for tight control on process parameters. Using Box-Behnken design of experiments, process optimization was performed for an optimal recipe for HfO2 films. UV treatment with in-situ processing of metal/high- dielectric stacks was studied to provide reduced variation in gate leakage current and capacitance. High-resolution transmission electron microscopy (TEM) was performed to calculate the equivalent oxide thickness (EOT) and dielectric constant of the films. Overall, this study shows that the in-situ fabrication of MIS gate stacks allows for lower processingcosts, high throughput, and superior device performance.

Keywords: gate stack, reliability, advanced CMOS, high-k, metal gate, Vt tuning, work function.

The purpose of this research has been to search for proper metallic gate electrodes for CMOS devices. This dissertation covers several binary alloy metal gate research topics. First, intermetallic binary alloy RuY was investigated. From C-V analysis we obtained the effective work function of Ru-Y thin films to range from 5.0eV to 3.9eV which is suitable for dual metal gate CMOS. The rich Y film was found to be not stable on SiO2 dielectrics because of the high oxygen affinity of Y. RuxYy thin film may still be a candidate for low temperature process, especially due to its large range of work function. More over, RuY has smaller grain size than Ru which demonstrates one of the advantages of alloy by reducing grain size to achieve more uniform gate film and more uniform effective work function for the nano-size device applications. Chapter 3 presents MoxTay as a potential candidate for dual metal CMOS applications. The electrical characterization results of MoTa alloy indicates that the effective work function can be controlled to around 4.3 eV on SiO2 and is suitable for NMOS gate electrode application. The MoTa alloy forms a solid solution instead of an intermetallic compound. We report that the MoTa solid solution can achieve low work function values and is stable up to 900 & deg;C. X-ray diffraction results indicated only a single MoTa alloy phase. Moreover, from Auger electron spectroscopy and Rutherford backscattering spectroscopy analysis, MoTa was found to be stable on SiO2 under high temperature anneals and no metal diffusion into substrate Si channel was detected. This indicates that MoxTay is a good candidate for CMOS metal gate applications. Chapter 4 evaluates Ru and W capping layer for MoTa metal gate electrodes in Metal Oxide Semiconductor capacitor applications. We report that the oxygen diffusion from the capping layer plays an important role in determining the MoTa alloy effective work function value on SiO2. MoTa alloy metal gate with Ru capping exhib.

This dissertation has focused on fabrication and characterization of alternative gate stacks consisting of high-K dielectrics and metal gates. This work has presented the evaluation of Ta based metals including Ta, TaNx, and TaSixNy as gate electrodes for their potential use in NMOS devices. For bulk CMOS devices, gate metals must have work functions that are near the conduction and valence band edges of Si. Although several metal gate electrodes have been identified for SiO2 dielectrics based on their work function, thermal stability and carrier concentration, their compatibility with high-K dielectrics is not fully understood. The questions that need to be addressed include thermal stability of metals on high-K, work function values, Fermi level pinning and performance. In this work, we report on the characteristics of metal gate electrodes on SiO2 and HfO2-based dielectrics with respect to equivalent oxide thickness (EOT), flatband voltage (VFB), leakage, work function and thermal stability. The research indicated that the workfunction of TaSixNy is compatible with NMOS devices, provided the right composition is achieved. The improved stability of TaSixNy gates is attributed to the presence of Si and N in the gate electrode, which can improve the film microstructure and the diffusion barrier properties at the gate-dielectric interface. This stability of TaSixNy films may enable high-k dielectrics and metallic electrode to be implemented in advanced CMOS devices. An equivalent oxide thickness of 11.2Å was obtained in TaSixNy /HfO2/p-Si MOS capacitor, while maintaining low leakage current density of 4.1 x 10-2A/cm2 at Vg-VFB=-1V in accumulation. A less EOT increase(~3 Å) was observed with TaSixNy gates compared to other gates (Ta, TaNx, and Ru) due to the excellent oxygen barrier properties of TaSixNy gates, preventing oxygen diffusion into the dielectric through gate electrode and dielectric during annealing. It was observed that trapped charge was incre.